// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

// --------------------------------------------------------------------------------

// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017

// Date        : Fri Mar 23 17:08:08 2018

// Host        : ubuntu running 64-bit Ubuntu 16.04.3 LTS

// Command     : write_verilog -force -mode synth_stub

//               /home/digilent/work/git/Zybo-base-linux/src/bd/system/ip/system_v_tc_out_0/system_v_tc_out_0_stub.v

// Design      : system_v_tc_out_0

// Purpose     : Stub declaration of top-level module interface

// Device      : xc7z010clg400-1

// --------------------------------------------------------------------------------

​

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

// Please paste the declaration into a Verilog source file or add the file as an additional source.

(* x_core_info = "v_tc,Vivado 2017.4" *)

module system_v_tc_out_0(clk, clken, s_axi_aclk, s_axi_aclken, gen_clken, 

  hsync_out, hblank_out, vsync_out, vblank_out, active_video_out, resetn, s_axi_aresetn, 

  s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, 

  s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, 

  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, irq, fsync_in, fsync_out)

/* synthesis syn_black_box black_box_pad_pin="clk,clken,s_axi_aclk,s_axi_aclken,gen_clken,hsync_out,hblank_out,vsync_out,vblank_out,active_video_out,resetn,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,irq,fsync_in,fsync_out[0:0]" */;

  input clk;

  input clken;

  input s_axi_aclk;

  input s_axi_aclken;

  input gen_clken;

  output hsync_out;

  output hblank_out;

  output vsync_out;

  output vblank_out;

  output active_video_out;

  input resetn;

  input s_axi_aresetn;

  input [8:0]s_axi_awaddr;

  input s_axi_awvalid;

  output s_axi_awready;

  input [31:0]s_axi_wdata;

  input [3:0]s_axi_wstrb;

  input s_axi_wvalid;

  output s_axi_wready;

  output [1:0]s_axi_bresp;

  output s_axi_bvalid;

  input s_axi_bready;

  input [8:0]s_axi_araddr;

  input s_axi_arvalid;

  output s_axi_arready;

  output [31:0]s_axi_rdata;

  output [1:0]s_axi_rresp;

  output s_axi_rvalid;

  input s_axi_rready;

  output irq;

  input fsync_in;

  output [0:0]fsync_out;

endmodule