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/* Generated by Yosys 0.19 (git sha1 a45c131b37c, clang 13.1.6 -fPIC -Os) */
module lakeroad_xilinx_ultrascale_plus_sub8_2(a, b, out0);
input [7:0] a;
wire [7:0] a;
input [7:0] b;
wire [7:0] b;
wire [7:0] co_3;
wire [7:0] luts_O5_0;
wire [7:0] luts_O6_1;
wire [7:0] o_2;
output [7:0] out0;
wire [7:0] out0;
LUT6_2 #(
.INIT(64'h9fffffff2fffffff)
) A_LUT_0 (
.I0(a[0]),
.I1(b[0]),
.I2(1'h1),
.I3(1'h1),
.I4(1'h1),
.I5(1'h1),
.O5(luts_O5_0[0]),
.O6(luts_O6_1[0])
);
) B_LUT_1 (
.I0(a[1]),
.I1(b[1]),
.O5(luts_O5_0[1]),
.O6(luts_O6_1[1])
) C_LUT_2 (
.I0(a[2]),
.I1(b[2]),
.O5(luts_O5_0[2]),
.O6(luts_O6_1[2])
) D_LUT_3 (
.I0(a[3]),
.I1(b[3]),
.O5(luts_O5_0[3]),
.O6(luts_O6_1[3])
) E_LUT_4 (
.I0(a[4]),
.I1(b[4]),
.O5(luts_O5_0[4]),
.O6(luts_O6_1[4])
) F_LUT_5 (
.I0(a[5]),
.I1(b[5]),
.O5(luts_O5_0[5]),
.O6(luts_O6_1[5])
) G_LUT_6 (
.I0(a[6]),
.I1(b[6]),
.O5(luts_O5_0[6]),
.O6(luts_O6_1[6])
) H_LUT_7 (
.I0(a[7]),
.I1(b[7]),
.O5(luts_O5_0[7]),
.O6(luts_O6_1[7])
CARRY8 carry_8 (
.CI(1'h1),
.CI_TOP(1'h0),
.CO(co_3),
.DI(luts_O5_0),
.O(out0),
.S(luts_O6_1)
assign o_2[7] = out0[7];
assign o_2[6] = out0[6];
assign o_2[5] = out0[5];
assign o_2[4] = out0[4];
assign o_2[3] = out0[3];
assign o_2[2] = out0[2];
assign o_2[1] = out0[1];
assign o_2[0] = out0[0];
endmodule
